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siv51001-3.4 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix iv device handbook volume 1 september 2012 feedback subscribe iso 9001:2008 registered 1. overview for the stratix iv device family altera ? stratix ? iv fpgas deliver a breakthrough level of system bandwidth and power efficiency for high-end applicatio ns, allowing you to innovate without compromise. stratix iv fpgas are based on the taiwan semiconductor manufacturing company (tsmc) 40-nm pr ocess technology and surpass all other high-end fpgas, with the highest logic dens ity, most transceivers, and lowest power requirements. the stratix iv device family contains thre e optimized variants to meet different application requirements: stratix iv e (enhanced) fpga s?up to 813,050 logic elements (les), 33,294 kilobits (kb) ram, and 1,288 18 x 18 bit multipliers stratix iv gx transceiver fpgas?up to 531,200 les, 27,376 kb ram, 1,288 18 x 18-bit multipliers, and 48 full-duplex clock data recovery (cdr)-based transceivers at up to 8.5 gbps stratix iv gt?up to 531,200 les, 27,376 kb ram, 1,288 18 x 18-bit multipliers, and 48 full-duplex cdr-based transceivers at up to 11.3 gbps the complete altera high-end solution includes the lowest risk, lowest total cost path to volume using hardcopy ? iv asics for all the family variants, a comprehensive portfolio of application so lutions customized for end-markets, and the industry leading quartus ? ii software to increase productivity and performance. f for information about upcoming stratix iv device features, refer to the upcoming stratix iv device features document. f for information about changes to the currently published stratix iv device handbook , refer to the addendum to the stratix iv device handbook chapter. this chapter contains the following sections: ?feature summary? on page 1?2 ?architecture features? on page 1?6 ?integrated software platform? on page 1?19 ?ordering information? on page 1?19 september 2012 siv51001-3.4
1?2 chapter 1: overview for the stratix iv device family feature summary stratix iv device handbook september 2012 altera corporation volume 1 feature summary the following list summarizes the stratix iv device family features: up to 48 full-duplex cdr-based transcei vers in stratix iv gx and gt devices supporting data rates up to 8.5 gbps and 11.3 gbps, respectively dedicated circuitry to support physical layer functionality for popular serial protocols, such as pci express (pcie) (pipe) gen1 and gen2, gbps ethernet (gbe), serial rapidio, sonet/sdh, xaui/higig, (oif) cei-6g, sd/hd/3g-sdi, fibre channel, sfi-5, and interlaken complete pcie protocol solution with embedded pcie hard ip blocks that implement phy-mac layer, data link laye r, and transaction layer functionality f for more information, refer to the ip compiler for pci express user guide . programmable transmitter pre-emphasis an d receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium typical physical medium attachment (pma) power consumption of 100 mw at 3.125 gbps and 135 mw at 6.375 gbps per channel 72,600 to 813,050 equivalent les per device 7,370 to 33,294 kb of enhanced trimatri x memory consisting of three ram block sizes to implement true dual-port memory and fifo buffers high-speed digital signal processing (dsp) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full -precision multipliers at up to 600 mhz up to 16 global clocks (gclk), 88 regional clocks (rclk), and 132 periphery clocks (pclk) per device programmable power technology that mini mizes power while maximizing device performance up to 1,120 user i/o pins arranged in 24 modular i/o banks that support a wide range of single-ended and differential i/o standards support for high-speed external memo ry interfaces including ddr, ddr2, ddr3 sdram, rldram ii, qdr ii, and qdr ii+ sram on up to 24 modular i/o banks high-speed lvds i/o support with seri alizer/deserializer (serdes), dynamic phase alignment (dpa), and soft-cdr ci rcuitry at data rates up to 1.6 gbps support for source-synchronous bus standards, including sgmii, gbe, spi-4 phase 2 (pos-phy level 4), sfi-4.1, xsbi, utopia iv, npsi, and csix-l1 pinouts for stratix iv e devices designed to allow migration of designs from stratix iii to stratix iv e with minimal pcb impact
chapter 1: overview for the stratix iv device family 1?3 feature summary september 2012 altera corporation stratix iv device handbook volume 1 stratix iv gx devices stratix iv gx devices provide up to 48 full-duplex cdr-based transceiver channels per device: thirty-two out of the 48 transceiver chan nels have dedicated physical coding sublayer (pcs) and physical medium at tachment (pma) circuitry and support data rates between 600 mbps and 8.5 gbps the remaining 16 transceiver channels have dedicated pma-only circuitry and support data rates between 600 mbps and 6.5 gbps 1 the actual number of transceiver channels pe r device varies with device selection. for more information about the exact transc eiver count in each device, refer to table 1?1 on page 1?11 . 1 for more information about transceiver architecture, refer to the transceiver architecture in stratix iv devices chapter. figure 1?1 shows a high-level stratix iv gx chip view. figure 1?1. stratix iv gx chip view (1) note to figure 1?1 : (1) resource counts vary with device selection, package selection, or both. general purpose i/o and memory interface 600 mbps-8.5 gbps cdr-based transceiver general purpose i/o and 150 mbps-1.6 gbps lvds interface with dpa and soft-cdr transceiver block transceiver block transceiver block transceiver block pci express hard ip block pci express hard ip block pci express hard ip block pci express hard ip block general purpose i/o and memory interface pll pll pll pll pll pll general purpose i/o and memory interface general purpose i/o and memory interface pll pll fpga fabric (logic elements, dsp, embedded memory, clock networks) transceiver block general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr pll pll pll pll transceiver block transceiver block transceiver block transceiver block general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr general purpose i/o and high-speed lvds i/o with dpa and soft cdr
1?4 chapter 1: overview for the stratix iv device family feature summary stratix iv device handbook september 2012 altera corporation volume 1 stratix iv e device stratix iv e devices provide an excellent solu tion for applications that do not require high-speed cdr-based transceivers, but are logic, user i/o, or memory intensive. figure 1?2 shows a high-level stratix iv e chip view. figure 1?2. stratix iv e chip view (1) note to figure 1?2 : (1) resource counts vary with device selection, package selection, or both. general purpose i/o and memory interface general purpose i/o and 150 mbps-1.6 gbps lvds interface with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and memory interface pll pll pll pll pll pll pll pll pll pll general purpose i/o and memory interface general purpose i/o and memory interface pll pll fpga fabric (logic elements, dsp, embedded memory, clock networks) general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr general purpose i/o and high-speed lvds i/o with dpa and soft-cdr
chapter 1: overview for the stratix iv device family 1?5 feature summary september 2012 altera corporation stratix iv device handbook volume 1 stratix iv gt devices stratix iv gt devices provide up to 48 cdr-based transceiver channels per device: thirty-two out of the 48 transceiver channels have dedicated pcs and pma circuitry and support data rates between 600 mbps and 11.3 gbps the remaining 16 transceiver channels have dedicated pma-only circuitry and support data rates between 600 mbps and 6.5 gbps 1 the actual number of transceiver channels pe r device varies with device selection. for more information about the exact transc eiver count in each device, refer to table 1?7 on page 1?16 . 1 for more information about stratix iv gt devices and transceiver architecture, refer to the transceiver architecture in stratix iv devices chapter. figure 1?3 shows a high-level stratix iv gt chip view. figure 1?3. stratix iv gt chip view (1) note to figure 1?3 : (1) resource counts vary with device selection, package selection, or both. general p u rpose i/o and memory interface 600 m b ps-11.3 g b ps cdr- b ased transcei v er general p u rpose i/o and u p to 1.6 g b ps l v ds interface w ith dpa and soft-cdr pci express hard ip block pci express hard ip block pci express hard ip block pci express hard ip block transcei v er block transcei v er block transcei v er block transcei v er block general p u rpose i/o and memory interface pll pll pll pll pll pll general p u rpose i/o and memory interface general p u rpose i/o and memory interface pll pll fpga fab r ic (logic elements, dsp, em b edded memory, clock n et w orks) transcei v er block general p u rpose i/o and high-speed l v ds i/o w ith dpa and soft cdr general p u rpose i/o and high-speed l v ds i/o w ith dpa and soft cdr pll pll pll pll general p u rpose i/o and high-speed l v ds i/o w ith dpa and soft cdr general p u rpose i/o and high-speed l v ds i/o w ith dpa and soft cdr general p u rpose i/o and high-speed l v ds i/o w ith dpa and soft cdr transcei v er block transcei v er block transcei v er block transcei v er block
1?6 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 architecture features the stratix iv device family features are di vided into high-speed transceiver features and fpga fabric and i/o features. 1 the high-speed transceiver features apply only to stratix iv gx and stratix iv gt devices. high-speed transceiver features the following sections describe high-speed transceiver features for stratix iv gx and gt devices. highest aggregate data bandwidth up to 48 full-duplex transceiver channels supporting data rates up to 8.5 gbps in stratix iv gx devices and up to 11.3 gbps in stratix iv gt devices. wide range of protocol support physical layer support for the following serial protocols: stratix iv gx?pcie gen1 and gen2, gbe, serial rapidio, sonet/sdh, xaui/higig, (oif) cei-6g, sd/hd/3g-s di, fibre channel, sfi-5, gpon, sas/sata, hypertransport 1.0 and 3.0, and interlaken stratix iv gt?40g/100g ethernet, sfi-s, interlaken, sfi-5.1, serial rapidio, sonet/sdh, xaui/higig, (oif) cei-6g, 3g-sdi, and fibre channel extremely flexible and easy-to-configure transceiver data path to implement proprietary protocols pcie support complete pcie gen1 and gen2 protoc ol stack solution compliant to pci express base specification 2.0 that includes phy-mac, data link, and transaction layer circuitry embedded in pci express hard ip blocks f for more information, refer to the pci express compiler user guide . root complex and end-point applications x1, x4, and x8 lane configurations pipe 2.0-compliant interface embedded circuitry to switch be tween gen1 and gen2 data rates built-in circuitry for electrical idle generation and detection, receiver detect, power state transitions, lane reversal, and polarity inversion 8b/10b encoder and decoder, receiver synchronization state machine, and 300 parts per million (ppm) cl ock compensation circuitry transaction layer support for up to two virtual channels (vcs)
chapter 1: overview for the stratix iv device family 1?7 architecture features september 2012 altera corporation stratix iv device handbook volume 1 xaui/higig support compliant to ieee802.3ae specification embedded state machine circuitry to convert xgmii idle code groups (||i||) to and from idle ordered sets (||a||, ||k||, ||r||) at the transmitter and receiver, respectively 8b/10b encoder and decoder, receiver synchronization state machine, lane deskew, and 100 ppm clock compensation circuitry gbe support compliant to ieee802.3-2005 specification automatic idle ordered set (/i1/, /i2/) generation at the transmitter, depending on the current running disparity 8b/10b encoder and decoder, receiver synchronization state machine, and 100 ppm clock compensation circuitry support for other protocol features su ch as msb-to-lsb transmission in sonet/sdh configuration and spread-spect rum clocking in pcie configurations diagnostic features serial loopback from the transmitter serial izer to the receiver cdr for transceiver pcs and pma diagnostics reverse serial loopback pre- and post-cdr to transmitter buffer for physical link diagnostics loopback master and slave capabili ty in pci express hard ip blocks f for more information, refer to the pci express compiler user guide . signal integrity stratix iv devices simplify the challenge of signal integrity through a number of chip, package, and board-level enhancements to enable efficient high-speed data transfer into and out of the device. these enhancements include: programmable 3-tap transmitter pre-emphas is with up to 8,192 pre-emphasis levels to compensate for pre-cursor and po st-cursor inter-symbol interference (isi) up to 900% boost capability on the first pre-emphasis post-tap user-controlled and adaptive 4-stage rece iver equalization with up to 16 db of high-frequency gain on-die power supply regulators for transmitter and receiver phase-locked loop (pll) charge pump and voltage controlled oscillator (vco) for superior noise immunity on-package and on-chip power supply deco upling to satisfy transient current requirements at higher frequencies, thereby reducing the need for on-board decoupling capacitors calibration circuitry for transmitter an d receiver on-chip termination (oct) resistors
1?8 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 fpga fabric an d i/o features the following sections describe the stratix iv fpga fabric and i/o features. device core features up to 531,200 les in stratix iv gx and gt devices and up to 813,050 les in stratix iv e devices, efficien tly packed in unique and innovative adaptive logic modules (alms) ten alms per logic array block (lab) deli ver faster performance, improved logic utilization, and optimized routing programmable power technology, including a variety of process, circuit, and architecture optimizations and innovations programmable power technology available to select power-driven compilation options for reduced static power consumption embedded memory trimatrix embedded memory architecture provides three different memory block sizes to efficiently address the needs of diversified fpga designs: 640-bit mlab 9-kb m9k 144-kb m144k up to 33,294 kb of embedded memory operating at up to 600 mhz each memory block is independently conf igurable to be a single- or dual-port ram, fifo, rom, or shift register digital signal processing (dsp) blocks flexible dsp blocks configurable as 9 x 9- bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 mhz with rounding and saturation capabilities faster operation due to fully pipelined architecture and built-in addition, subtraction, and accumulation units to combine multiplication results optimally designed to support advanced features such as adaptive filtering, barrel shifters, and finite and infinite impulse response (fir and iir) filters clock networks up to 16 global clocks and 88 regional clocks optimally routed to meet the maximum performance of 800 mhz up to 112 and 132 periphery clocks in stratix iv gx and stratix iv e devices, respectively up to 66 (16 gclk + 22 rclk + 28 pclk) clock networks per device quadrant in stratix iv gx and stratix iv gt devices up to 71 (16 gclk + 22 rclk + 33 pclk) clock networks per device quadrant in stratix iv e devices
chapter 1: overview for the stratix iv device family 1?9 architecture features september 2012 altera corporation stratix iv device handbook volume 1 plls three to 12 plls per device support ing spread-spectrum input tracking, programmable bandwidth, clock switchov er, dynamic reconfiguration, and delay compensation on-chip pll power supply regulators to minimize noise coupling i/o features sixteen to 24 modular i/o banks per device with 24 to 48 i/os per bank designed and packaged for optimal simultaneous switching noise (ssn) performance and migration capability support for a wide range of industry i/o standards, including single-ended (lvttl/cmos/pci/pcix), differential (lvds/mini-lvds/rsds), voltage-referenced single-ended and di fferential (sstl/hstl class i/ii) i/o standards on-chip series (r s ) and on-chip parallel (r t ) termination with auto-calibration for single-ended i/os and on-chip differential (r d ) termination for differential i/os programmable output drive strength, slew rate control, bus hold, and weak pull-up capability fo r single-ended i/os user i/o:gnd:v cc ratio of 8:1:1 to reduce loop inductance in the package?pcb interface programmable transmitter differential output voltage (v od ) and pre-emphasis for high-speed lvds i/o high-speed differential i/o with dpa and soft-cdr dedicated circuitry on the left and right si des of the device to support differential links at data rates from 150 mbps to 1.6 gbps up to 98 differential serdes in strati x iv gx devices, up to 132 differential serdes in stratix iv e devices, and up to 47 differential serdes in stratix iv gt devices dpa circuitry at the receiver automati cally compensates for channel-to-channel and channel-to-clock skew in source synchronous interfaces soft-cdr circuitry at the receiver allows implementation of asynchronous serial interfaces with embedded clocks at up to 1.6 gbps data rate (sgmii and gbe) external memory interfaces support for existing and emerging memo ry interface standards such as ddr sdram, ddr2 sdram, ddr3 sdram, qdrii sram, qdrii+ sram, and rldram ii ddr3 up to 1,067 mbps/533 mhz programmable dq group widths of 4 to 36 bits (includes parity bits) dynamic oct, trace mismatch compensati on, read-write leveling, and half-rate register capabilities provide a robust external memory interface solution
1?10 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 system integration all stratix iv devices support hot socketing four configuration modes: passive serial (ps) fast passive parallel (fpp) fast active serial (fas) jtag configuration ability to perform remote system upgrades 256-bit advanced encryption standard (a es) encryption of configuration bits protects your design against copying, reverse engineering, and tampering built-in soft error detection for configuration ram cells f for more information about how to connect th e pll, external memory interfaces, i/o, high-speed differential i/o, power, and the jtag pins to pcb, refer to the stratix iv gx and stratix iv e device family pin connection guidelines and the stratix iv gt device family pin connection guidelines .
chapter 1: overview for the stratix iv device family 1?11 architecture features september 2012 altera corporation stratix iv device handbook volume 1 table 1?1 lists the stratix iv gx device features. table 1?1. stratix iv gx device features (part 1 of 2) feature ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 package option f780 f1152 f780 f1152 f780 f1152 f1517 f780 f1152 f1517 f780 f1152 f1517 f1760 f1932 f780 f1152 f1517 f1760 f1932 f1760 f1932 alms 29,040 42,240 70,300 91,200 116,480 141,440 212,480 les 72,600 105,600 175,750 228,000 291,200 353,600 531,200 0.6 gbps- 8.5 gbps transceivers (pma + pcs) (1) ? 16 ? ? 16 ? ?1624 ? ? 1624 ? ? 16242432 ? ? 162424 32 24 32 0.6 gbps- 6.5 gbps transceivers (pma + pcs) (1) 8 ? 8 16 ? 8 16 ? ? 8 16 ? ? 16 16 ? ? ? ? 16 16 ? ? ? ? ? ? pma-only cmu channels (0.6 gbps- 6.5 gbps) ? 8 ? ? 8 ? ? 8 12 ? ? 8 12 ? ? 8 12 12 16 ? ? 8 12 12 16 12 16 pci express hard ip blocks 121 2 1 2 1 2 2 4 2 4 4 high-speed lvds serdes (up to 1.6 gbps) (4) 28 56 28 28 56 28 44 88 28 44 88 ? 44 88 88 98 ? 44 88 88 98 88 98 spi-4.2 links 1 1 1 2 4 1 2 4 ? 2 4 ? 2 4 4
1?12 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 m9k blocks (256 x 36 bits) 462 660 950 1,235 936 1,248 1,280 m144k blocks (2048 x 72 bits) 16 16 20 22 36 48 64 total memory (mlab+m9k +m144k) kb 7,370 9,564 13,627 17,133 17,248 22,564 27,376 embedded multipliers 18 x 18 (2) 384 512 920 1,288 832 1,040 1,02 4 1,024 plls 3 4 3 4 3 6 8 3 6 8 4 6 8 12 12 4 6 8 12 12 12 12 user i/os (3) 372 488 372 372 48 8 372 56 4 56 4 74 4 372 564 56 4 74 4 289 564 56 4 74 4 88 0 92 0 289 564 56 4 74 4 88 0 920 880 920 speed grade (fastest to slowest) (5) ?2 ? , ?3, ?4 ?2, ?3, ?4 ?2 ? , ?3, ?4 ?2 ? , ?3, ?4 ?2, ?3, ?4 ?2 ? , ?3, ?4 ?2 ? , ?3, ?4 ?2 , ?3 , ?4 ?2, ?3, ?4 ?2 ? , ?3, ?4 ?2 ? , ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2 ? , ?3, ?4 ?2 ? , ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2 ? , ?3, ?4 ?2 ? , ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 notes to table 1?1 : (1) the total number of transceivers is divided equally between the left and right side of each device, except for the devices i n the f780 package. these d evices have eight transceiver channels located only on the right side of the device. (2) four multiplier adder mode. (3) the user i/os count from pin-out fil es includes all general purpose i/o, dedicated clock pins, and dual purpose configuratio n pins. transceiver pins and dedicated c onfiguration pins are not included in the pin count. (4) total pairs of high-speed lvds serd es take the lowest channel count of r x /t x . (5) the difference between the st ratix iv gx devices in the ?2 and ?2x speed grades is th e number of available transceiver chann els. the ?2 device allows you to use the transceiver cmu blocks as transceiver channels. the ?2x device does no t allow you to use th e cmu blocks as transceiver channe ls. in addition to the reduc tion of available transcei ver channels in the stra tix iv gx ?2x device, the data rates in the ?2x d evice are limited to 6.5 gbps. table 1?1. stratix iv gx device features (part 2 of 2) feature ep4sgx70 ep4sgx110 ep4sgx180 ep4sgx230 ep4sgx290 ep4sgx360 ep4sgx530 package option f780 f1152 f780 f1152 f780 f1152 f1517 f780 f1152 f1517 f780 f1152 f1517 f1760 f1932 f780 f1152 f1517 f1760 f1932 f1760 f1932
chapter 1: overview for the stratix iv device family 1?13 architecture features september 2012 altera corporation stratix iv device handbook volume 1 table 1?2 lists the stratix iv gx device package options. 1 on-package decoupling reduces the need for on-board or pcb decoupling capacitors by sati sfying the transient current requirements at higher frequencies. the power delivery network design tool for stratix iv devices accounts for the on-package decoupling and reflects the reduced requ irements for pcb decoupling capacitors. table 1?2. stratix iv gx device package options (1) , (2) device f780 (29 mm x 29 mm) (6) f1152 (35 mm x 35 mm) (6) f1152 (35 mm x 35 mm) (5) , (7) f1517 (40 mm x 40 mm) (5) , (7) f1760 (42.5 mm x 42.5 mm) (7) f1932 (45 mm x 45 mm) (7) ep4sgx70 df29 ? ? hf35 ? ? ? ? ep4sgx110 df29 ? ff35 hf35 ? ? ? ? ep4sgx180 df29 ? ff35 ? hf35 kf40 ? ? ep4sgx230 df29 ? ff35 ? hf35 kf40 ? ? ep4sgx290 ? fh29 (3) ff35 ? hf35 kf40 kf43 nf45 ep4sgx360 ? fh29 (3) ff35 ? hf35 kf40 kf43 nf45 ep4sgx530 ? ? ? ? hh35 (4) kh40 (4) kf43 nf45 notes to table 1?2 : (1) device packages in the same column and marked under the same arro w sign have vertical migration capability. (2) use the pin migration viewer in the pi n planner to verify the pin mi gration compatibility when mi grating devices. for more i nformation, refer to i/o management in the quartus ii handbook, volume 2 . (3) the 780-pin ep4sgx290 and ep4sgx360 devices are availa ble only in 33 mm x 33 mm hy brid flip ch ip package. (4) the 1152-pin and 1517-pin ep4sgx530 devices are available only in 42 .5 mm x 42.5 mm hybrid flip chip packages. (5) when migrating between hybrid and flip chip packages, there is an ad ditional keep-out area. for more information, refer to t he package information dat asheet for altera devices . (6) devices listed in this column are avai lable in ?2x, ?3, and ?4 speed grades. these devices do no t have on-package decoupling capacitors. (7) devices listed in this column are ava ilable in ?2, ?3, and ?4 sp eed grades. these devices have on-package decoupling capacit ors. for more information about on-package decoupli ng capacitor value in each device, refer to table 1?3 .
1?14 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 table 1?3 lists the stratix iv gx device on-package decoupling information. table 1?3. stratix iv gx device on-package decoupling information (1) ordering information v cc v ccio v ccl_gxb v cca_l/r v cct and v ccr (shared) ep4sgx70 hf35 2 ? 1uf + 2 ? 470nf 10nf per bank (2) 100nf per transceiver block 100nf 1 ? 470nf + 1 ? 47nf per side ep4sgx110 hf35 2 ? 1uf + 2 ? 470nf 10nf per bank (2) 100nf per transceiver block 100nf 1 ? 470nf + 1 ? 47nf per side ep4sgx180 hf35 kf40 2 ? 1uf + 2 ? 470nf 10nf per bank (2) 100nf per transceiver block 100nf 1 ? 470nf + 1 ? 47nf per side ep4sgx230 hf35 kf40 2 ? 1 uf + 2 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 1 ? 470 nf + 1 ? 47 nf per side ep4sgx290 hf35 kf40 kf43 nf45 4 ? 1 uf + 4 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100nf 1 ? 470 nf + 1 ? 47 nf per side ep4sgx360 hf35 kf40 kf43 nf45 4 ? 1 uf + 4 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 1 ? 470 nf + 1 ? 47 nf per side ep4sgx530 hh35 kh40 kf43 nf45 4 ? 1 uf + 4 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 1 ? 470 nf + 1 ? 47 nf per side notes to table 1?3 : (1) table 1?3 refers to production devices on-package dec oupling. for more informatio n about decoupling d esign of engineering sample (es) de vices, contact altera technical support . (2) for i/o banks 3(*), 4(*), 7(*), and 8(*) only. ther e is no opd for i/o bank 1(*), 2(*), 5(*), and 6(*).
chapter 1: overview for the stratix iv device family 1?15 architecture features september 2012 altera corporation stratix iv device handbook volume 1 table 1?4 lists the stratix iv e device features. table 1?4. stratix iv e device features feature ep4se230 ep4se360 ep4se530 ep4se820 package pin count 780 780 1152 1152 1517 1760 1152 1517 1760 alms 91,200 141,440 212,480 325,220 les 228,000 353,600 531,200 813,050 high-speed lvds serdes (up to 1.6 gbps) (1) 56 56 88 88 112 112 88 112 132 spi-4.2 links 3 3 4 4 6 4 6 6 m9k blocks (256 x 36 bits) 1,235 1,248 1,280 1610 m144k blocks (2048 x 72 bits) 22 48 64 60 total memory (mlab+m9k+ m144k) kb 17,133 22,564 27,376 33,294 embedded multipliers (18 x 18) (2) 1,288 1,040 1,024 960 plls 4 4 8 8 12 12 8 12 12 user i/os (3) 488 488 744 744 976 976 744 (4) 976 (4) 1120 (4) speed grade (fastest to slowest) ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?2, ?3, ?4 ?3, ?4 ?3, ?4 ?3, ?4 notes to table 1?4 : (1) the user i/o count from the pin-out files include all general purpose i/os, dedicated clock pins, and dual purpose configura tion pins. transceiver pins and dedicated configuration pins are not included in the pin count. (2) four multiplier adder mode. (3) total pairs of high-speed lvds serd es take the lowest channel count of r x /t x . (4) this data is preliminary.
1?16 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 table 1?5 summarizes the stratix iv e device package options. table 1?6 lists the stratix iv e on-package decoupling information. table 1?7 lists the stratix iv gt device features. table 1?5. stratix iv e device package options (1) , (2) device f780 (29 mm x 29 mm) (5) , (6) f1152 (35 mm x 35 mm) (5) , (7) f1517 (40 mm x 40 mm) (7) f1760 (42.5 mm x 42.5 mm) (7) ep4se230 f29 ? ? ? ep4se360 h29 (3) f35 ? ? ep4se530 ? h35 (4) h40 (4) f43 ep4se820 ? h35 (4) h40 (4) f43 notes to table 1?5 : (1) device packages in the same column and marked under the same arrow sign have vertical migration capability. (2) use the pin migration viewer in the pin planner to verify the pi n migration compatibility when migrating devices. for more i nformation, refer to i/o management in the quartus ii handbook, volume 2 . (3) the 780-pin ep4se360 device is available only in the 33 mm x 33 mm hybrid flip chip package. (4) the 1152-pin and 1517-pin fo r ep4se530 and ep4se820 devices are available only in the 42.5 mm x 42.5 mm hybrid flip chip package . (5) when migrating between hybrid and flip ch ip packages, there is an ad ditional keep-out area. for mo re information, refer to t he package information datasheet for altera devices . (6) devices listed in this column do not have on-package decoupling capacitors. (7) devices listed in this column have on -package decoupling capacitors. for more information about on-package decoupling capaci tor value for each device, refer to table 1?6 . table 1?6. stratix iv e device on-package decoupling information (1) ordering information v cc v ccio ep4se360 f35 4 ? 1 uf + 4 ? 470 nf 10 nf per bank ep4se530 h35 h40 f43 4 ? 1 uf + 4 ? 470 nf 10 nf per bank ep4se820 h35 h40 f43 4 ? 1 uf + 4 ? 470 nf 10 nf per bank note to table 1?6 : (1) table 1?6 refers to production devices on-package d ecoupling. for more informat ion about deco upling design of engi neering sample (es) devices, contact altera technical support . table 1?7. stratix iv gt device features (part 1 of 2) feature ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g3 ep4s100g4 ep4s100g5 package pin count 1517 1517 1517 1932 1932 1517 1932 alms 91,200 212,480 91,200 116,480 141,440 212,480 les 228,000 531,200 228,000 291,200 353,600 531,200 total transceiver channels 36 36 36 48 48 36 48
chapter 1: overview for the stratix iv device family 1?17 architecture features september 2012 altera corporation stratix iv device handbook volume 1 10g transceiver channels (600 mbps - 11.3 gbps with pma + pcs) 12 12 24 24 24 24 32 8g transceiver channels (600 mbps - 8.5 gbps with pma + pcs) (1) 12 12 0 8 8 0 0 pma-only cmu channels (600 mbps- 6.5 gbps) 12 12 12 16 16 12 16 pcie hard ip blocks 2 2 2 4 4 2 4 high-speed lvds serdes (up to 1.6 gbps) (2) 46 46 46 47 47 46 47 sp1-4.2 links 2 2 2 2 2 2 2 m9k blocks (256 x 36 bits) 1,235 1,280 1,235 936 1,248 1,280 m144k blocks (2048 x 72 bits) 22 64 22 36 48 64 total memory (mlab + m9k + m144k) kb 17,133 27,376 17,133 17,248 22,564 27,376 embedded multipliers 18 x 18 (3) 1,288 1,024 1,288 832 1,024 1,024 plls 8 8 8 12 12 8 12 user i/os (4) , (5) 654 654 654 781 781 654 781 speed grade (fastest to slowest) ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 notes to table 1?7 : (1) you can configure all 10g tr ansceiver channels as 8g transcei ver channels. for example, the ep 4s40g2f40 device has twenty-fo ur 8g transceiver channels and the ep4s100g5f45 devi ce has thirty-two 8g transceiver channels. (2) total pairs of high-speed lvds serd es take the lowest channel count of r x /t x . (3) four multiplier adder mode. (4) the user i/o count from the pin-out files include all genera l purpose i/os, dedicated clock pins, and dual purpose configura tion pins. transceiver pins and dedicated configuration pins are not included in the pin count. (5) this data is preliminary. table 1?7. stratix iv gt device features (part 2 of 2) feature ep4s40g2 ep4s40g5 ep4s100g2 ep4s100g3 ep4s100g4 ep4s100g5
1?18 chapter 1: overview for the stratix iv device family architecture features stratix iv device handbook september 2012 altera corporation volume 1 table 1?8 lists the resource counts for the stratix iv gt devices. table 1?9 lists the stratix iv gt on-package decoupling information. table 1?8. stratix iv gt device package options (1) , (2) device 1517 pin (40 mm x 40 mm) (3) 1932 pin (45 mm x 45 mm) stratix iv gt 40 g devices ep4s40g2 f40 ? ep4s40g5 h40 (4) , (5) ? stratix iv gt 100 g devices ep4s100g2 f40 ? ep4s100g3 ? f45 ep4s100g4 ? f45 ep4s100g5 h40 (4) , (5) f45 notes to table 1?8 : (1) this table represents pin compatability; however, it does not includ e hard ip block placement compatability. (2) devices under the same arrow sign have vertical migration capability. (3) when migrating between hybrid and flip chip packages, there is an additional keep-out area. for more information, refer to the altera device package information data sheet . (4) ep4s40g5 and ep4s100g 5 devices with 1517 pi n-count are only available in 42.5- mm x 42.5-mm hybr id flip chip packages. (5) if you are using the hard ip block, migration is not possible. table 1?9. stratix iv gt device on-package decoupling information (1) ordering information v cc v ccio v ccl_gxb v cca_l/r v cct_l/r v ccr_l/r ep4s40g2f40 ep4s100g2f40 2 ? 1 uf + 2 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 100 nf 100 nf ep4s100g3f45 4 ? 1 uf + 4 ? 470 nf 10 nf per bank (2) 100 nf per transceiver block 100 nf 100 nf 100 nf ep4s100g4f45 ep4s40g5h40 ep4s100g5h40 ep4s100g5f45 notes to table 1?9 : (1) table 1?9 refers to production devices on-package d ecoupling. for more informat ion about deco upling design of engi neering sample (es) devices, contact altera technical support . (2) for i/o banks 3(*), 4(*), 7(*), and 8(*) only. there is no opd for i/o bank 1(*), 2(*), 5(*), and 6(*).
chapter 1: overview for the stratix iv device family 1?19 integrated software platform september 2012 altera corporation stratix iv device handbook volume 1 integrated software platform the quartus ii software provides an integrated environment for hdl and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, signaltap ii logic analyzer, and de vice configuration of stratix iv designs. the quartus ii software provides the megawizard ? plug-in manager user interface to generate different functional blocks, such as memory, pll, and digital signal processing logic. for transceivers, the quartus ii software provides the altgx megawizard plug-in manager interface that guides you through configuration of the transceiver based on your application requirements. the stratix iv gx and gt transceivers allow you to implement low-power and reliable high-speed serial interface applications with its fully reconfigurable hardware, optimal signal integrity, and integrated quartus ii software platform. f for more information about the quartus ii software features, refer to the quartus ii handbook . ordering information this section describes the stratix iv e, gt, and gx devices ordering information. figure 1?4 shows the ordering codes for stratix iv gx and e devices. figure 1?4. stratix iv gx and e device packaging ordering information device density transceiver count package type 2, 2x, 3, or 4, w ith 2 b eing the fastest corresponds to pin count 29 = 780 pins 35 = 1152 pins 40 = 1517 pins 43 = 1760 pins 45 = 1932 pins f: fineline bga (fbga) h: hy b rid fineline bga ep4sgx: stratix i v transcei v er d: 8 f: 16 h: 24 k: 36 n : 4 8 ep4se: stratix i v logic/memory 70 110 1 8 0 230 290 360 530 8 20 optional suffix fam i l y s i g n a t u r e operating temperature sp e e d gr ad e ball array dimension 2 ep4sgx 230 c 40 f k es indicates specific de v ice options n :lead-free de v ices es: engineering sample c: commercial temperat u re (t j =0 c to 8 5 c) i: ind u strial temperat u re (t j =?40 c to 100 c) m: military temperat u re (t j =?55 c to 125 c)
1?20 chapter 1: overview for the stratix iv device family ordering information stratix iv device handbook september 2012 altera corporation volume 1 figure 1?5 shows the ordering codes for stratix iv gt devices. document revision history table 1?10 lists the revision history for this chapter. figure 1?5. stratix iv gt device packaging ordering information o device density package type 1, 2, 3 w ith 1 b eing the fastest corresponds to pin co u nt 40 = 1517 pins 45 = 1932 pins f: fineline bga (fbga) h: hy b rid fineline bga 2 = 230k les 3 = 290k les 4 = 360k les 5 = 530k les c: commercial temperature (t j =0 cto85 c) indust rial t emperat ure (t j = 0c to 100c) optional suffix fam i l y s i g n a t u r e operating temperature sp eed gr ade ball array dimension 2 ep4s 230 c 40 f es indicat es specific device opt ions n: lead-free devices i: es: engineering sample aggregate bandwidth ep4s 2 40g 40g 100g table 1?10. document revision history (part 1 of 2) date version changes september 2012 3.4 updated table 1?1 to close fb #30986. updated table 1?2 and table 1?5 to close fb #31127. june 2011 3.3 added military temperature to figure 1?4. february 2011 3.2 updated table 1?7 and table 1?8. applied new template. minor text edits. march 2010 3.1 updated table 1?1, table 1?2, and table 1?7. updated figure 1?3. updated the ?stratix iv gt devices? section. added two new references to the introduction section. minor text edits.
chapter 1: overview for the stratix iv device family 1?21 ordering information september 2012 altera corporation stratix iv device handbook volume 1 november 2009 3.0 updated the ?stratix iv device family overview?, ?feature summary?, ?stratix iv gt devices?, ?high-speed transceive r features?, ?fpga fabric and i/o features?, ?highest aggregate data bandwidth?, ?system integr ation?, and ?integrated software platform? sections. added table 1?3, table 1?6, and table 1?9. updated table 1?1, table 1?2, table 1?4, table 1?5, table 1?7, and table 1?8. updated figure 1?3, figure 1?4, and figure 1?5. minor text edits. june 2009 2.4 updated table 1?1. minor text edits. april 2009 2.3 added table 1?5, table 1?6, and figure 1?3. updated figure 1?5. updated table 1?1, table 1?2, table 1?3, and table 1?4. updated ?introduction?, ?feature summary?, ?stratix iv gx devices?, ?stratix iv gt devices?, ?architecture features?, and ?fpga fabric and i/o features? march 2009 2.2 updated ?feature summary?, ?stratix iv gx de vices?, ?stratix iv e device?, ?stratix iv gt devices?, ?signal integrity? removed tables 1-5 and 1-6 updated figure 1?4 march 2009 2.1 updated ?introduction?, ?feature summary?, ?s tratix iv device diagnostic features?, ?signal integrity?, ?clock networks?,?high-sp eed differential i/o with dpa and soft- cdr?, ?system integration?, and ?ordering information? sections. added ?stratix iv gt 100g devices? and ?stratix iv gt 100g transceiver bandwidth? sections. updated table 1?1, table 1?2, table 1?3, and table 1?4. added table 1?5 and table 1?6. updated figure 1?3 and figure 1?4. added figure 1?5. removed ?referenced documents? section. november 2008 2.0 updated ?feature summary? on page 1?1. updated ?stratix iv device diagnostic features? on page 1?7. updated ?fpga fabric and i/o features? on page 1?8. updated table 1?1. updated table 1?2. updated ?table 1?5 shows the total number of transceivers available in the stratix iv gt device.? on page 1?15. july 2008 1.1 revised ?introduction?. may 2008 1.0 initial release. table 1?10. document revision history (part 2 of 2) date version changes
1?22 chapter 1: overview for the stratix iv device family ordering information stratix iv device handbook september 2012 altera corporation volume 1
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